Post by account_disabled on Jan 29, 2024 1:00:20 GMT -5
Synopsys announced on Tuesday that it has reached a definitive agreement to acquire Ansys in a deal worth $35 billion. Synopsys mainly specializes in electronic design automation (EDA) tools and hardware intellectual property (IP) development, while Ansys develops electronics design analysis and simulation tools, so the deal creates a chip design software powerhouse with expertise in multiple industries. . Chip development is becoming increasingly difficult these days as the evolution of process technologies slows down and the number of transistors increases. To achieve optimal power, performance and area (PPA) results, chip designers today must work closely with foundries to optimize their design and processing technology, an approach known as design-technology co-optimization (DTCO).
In the future, chip Fax Lists designers must build multi-chiplet solutions to better address demanding applications, go beyond DTCO and optimize their solutions at the system level, an approach called system technology co-optimization (STCO). This is where Ansys design analysis and simulation will come in handy for customers using Synopsys' EDA tools. When they are fully integrated with Synopsys software (especially those enhanced with artificial intelligence), the company can offer a software package for designing next-generation processors and systems. This will greatly strengthen its competitive position against competitors such as Cadence and Siemens EDA. Meanwhile, Synopsys and Ansys have been collaborating since 2017, so the two companies' tools already provide a convenient development flow.
The megatrends of AI, the proliferation of silicon and software-defined systems demand greater computational efficiency and efficiency in the face of increasing system complexity," said Sassin Ghazi, president and CEO of Synopsys. "Combining Synopsys' advanced EDA solutions with Ansys' world-class simulation and analysis capabilities enables us to provide a comprehensive, powerful and seamlessly integrated silicon to systems approach to innovation to maximize the capabilities of R&D teams around the world." It's the next logical step in our successful, seven-year partnership with Ansys. Under the terms of the deal, Ansys shareholders will receive $197.00 in cash and 0.3450 Synopsys shares per Ansys share, valuing Ansys at approximately $35 billion based on Synopsys' stock price as of December 21, 2023.
In the future, chip Fax Lists designers must build multi-chiplet solutions to better address demanding applications, go beyond DTCO and optimize their solutions at the system level, an approach called system technology co-optimization (STCO). This is where Ansys design analysis and simulation will come in handy for customers using Synopsys' EDA tools. When they are fully integrated with Synopsys software (especially those enhanced with artificial intelligence), the company can offer a software package for designing next-generation processors and systems. This will greatly strengthen its competitive position against competitors such as Cadence and Siemens EDA. Meanwhile, Synopsys and Ansys have been collaborating since 2017, so the two companies' tools already provide a convenient development flow.
The megatrends of AI, the proliferation of silicon and software-defined systems demand greater computational efficiency and efficiency in the face of increasing system complexity," said Sassin Ghazi, president and CEO of Synopsys. "Combining Synopsys' advanced EDA solutions with Ansys' world-class simulation and analysis capabilities enables us to provide a comprehensive, powerful and seamlessly integrated silicon to systems approach to innovation to maximize the capabilities of R&D teams around the world." It's the next logical step in our successful, seven-year partnership with Ansys. Under the terms of the deal, Ansys shareholders will receive $197.00 in cash and 0.3450 Synopsys shares per Ansys share, valuing Ansys at approximately $35 billion based on Synopsys' stock price as of December 21, 2023.